1. Field
The following description relates to a processor for executing instructions, and more particularly to a pipeline processor.
2. Description of the Related Art
In a pipeline processor, one instruction is processed through several stages. For example, a process of processing an instruction may be separated into a fetch stage, a decode stage, an execute stage, a memory access stage, and a write stage. A plurality of instructions may be executed in parallel while sequentially passing through the respective stages of a pipeline processor so that a program may be processed more efficiently in comparison to a non-pipeline processor.
Factors affecting the performance of a pipeline processor include a branch hazard or a pipeline control hazard. The branch hazard indicates that the processing speed of a pipeline processor is deteriorating due to a branch instruction. Because a pipeline processor cannot obtain the address of an instruction to be fetched until the decode stage of a branch instruction is completed or the execute stage is performed, the branch instruction may deteriorate the performance of the pipeline processor, because the processor is delayed. Research for removing the branch hazard of a pipeline processor is underway, and techniques such as dynamic branch prediction, delayed branch, and static branch prediction have been suggested.
Meanwhile, in a reconfigurable processor, a coarse-grained array (CGA) accelerates loops involving a large amount of data operations and performs the operations, while a very long instruction word (VLIW) machine executes a control part. Generally, the control part has a small basic block (BB) and simple data flow. In the VLIW machine, an instruction execution schedule is determined by a compiler, which is software outside the processor. Meanwhile, the execution schedule inside the processor is fixed allowing the hardware to be simplified.
Among the above-mentioned techniques for mitigating the branch hazard, the dynamic branch prediction technique predicts the corresponding conditional branch instruction as taken or not-taken, depending on a history. The dynamic branch prediction technique occurs while a program is being executed. The dynamic branch prediction technique requires a great deal of hardware to solve the branch problem, and is not an ideal solution for removing the pipeline control hazard of a VLIW machine that has a simple hardware constitution. Also, the delay branch technique has a small BB and is not ideal for a VLIW machine that usually processes a large instruction into a number of small instructions.
In the static branch prediction technique, a conditional branch instruction is predicted as taken or not-taken before a program is executed. According to a conventional static branch prediction technique, a delay slot is not used when a conditional branch instruction is predicted as not-taken, and a delay slot is included behind a conditional branch instruction when the conditional branch instruction is predicted as taken. Thus, it is also difficult to apply the conventional static branch prediction technique to a VLIW machine. Furthermore, the conventional static branch prediction technique requires a large amount of information (data) to perform a branch operation and must perform many tasks, for example, a comparison process, a branch process, and the like. Thus, processing of a branch instruction may result in the lack of encoding space.